The present invention relates to a clock recovery circuit or a clock recovery unit suitable for high-speed differential interface.
IEEE 1394.b standard defines small-amplitude differential serial data transfer. A clock recovery technique for recovering, from a data signal, a clock that is synchronized with the data signal is required for a receiving unit used in such serial data transfer.
An example of a conventional clock recovery technique is shown in D. H. Wolaver, “Phase-Locked Loop circuit Design”, Section 10–2, pp. 213–216, Prentice Hall (1991). In this example, the format of a data signal is converted from NRZ (non-return-to-zero) to RZ (return-to-zero), and then a clock is recovered from the RZ data signal with a PLL (phase-locked loop).
Basically, an H level duration and an L level duration of an NRZ data signal are both an integer multiple of one data interval. However, the H level duration, for example, may become shorter than one data interval due to a skew occurring in a differential amplifier or a differential transfer path, or due to process variations. In such a case, with the conventional example, a timing jitter occurs in the recovered clock.
Moreover, with the conventional example, a phase detector and a charge pump of the PLL need to update the respective outputs for each data interval, whereby the operating speed of these elements limits the data rate.